Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors.
Some system designs employ a combination of hardware configured using the programmable logic of an FPGA and software running on a processor embedded within the FPGA. The most frequent use model is that of the hardware accelerator, in which a logic circuit configured using programmable logic acts as a programmable adjunct to a host processor. The hardware accelerator is used to tackle sub-problems that have been identified as computational bottlenecks in the host processor's software. Another emerging use model is that of a software assistant, in which the processor acts as a computational adjunct to a logic circuit configured in programmable logic. This use model essentially allows software procedure calls to be made from programmed logic.
The main benefits of using the software assistant model lie in using an embedded processor to save logic resources in the PLD and in simplifying design and verification. However, both the software assistant model and the hardware accelerator model are affected by the logic-processor interface. Notably, a bottleneck at the logic-processor interface deleteriously affects the performance of both the hardware accelerator model and the software assistant model. Accordingly, there exists a need in the art for an efficient method and apparatus for providing an interface between a logic circuit and a processor.